Worth the Squeeze: Circuits, Sensors, and Heterogeneous Packaging Approaches for Lab-on-CMOS Applications

The Lab-on-CMOS research community leverages the power and economies of scale of modern silicon integrated circuits, built up over the previous fifty years for high-performance computation and imaging, for low-cost chemical and biological sensing applications. The integration of new materials, sensing modalities, and intelligent computation in CMOS-based sensor platforms enable a broad range of miniaturized diagnostic, therapeutic, and continuous monitoring systems. 

The integration of fluid samples with silicon integrated circuit (IC) sensors is manageable in a laboratory setting through heterogeneous approaches, but a reliable, manufacturable fluid-IC interface solution continues to elude the Lab-on-CMOS community. The primary challenge is the need to integrate microfluidic channels on a chip surface that (due to wire bonds) is not planar. In addition, the area required for fluidic interconnect to an IC is cost prohibitive due to the large die area required to make a fluidic connection. In a new approach, we leverage fan-out wafer-level packaging (FOWLP) to co-locate ICs, sensors, and metallization in a planar substrate, combined with planar microfluidic delivery. This presentation will focus on Lab-on-CMOS SoC platforms demonstrated using custom IC sensors, heterogeneous integration, and post-fabrication to form electrical and fluidic connections to embedded sensor ICs.

The method we present will enable a broad new paradigm of reconfigurable lab-on-chip applications, analogous to system-on-chip (SoC) reconfigurable design. In the future, a library of detector ICs, microfluidic actuator chips, signal processing ICs, and data transceivers could be arranged in any permutation, over-molded to form a planar substrate, and integrated with microfluidic channels on top; this technique also enables co-integration of devices that cannot be manufactured in the same process.