An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Francesco Conti; Robert Schilling; Pasquale Davide Schiavone; Antonio Pullini; Davide Rossi ; Frank Kağan Gürkaynak; Michael Muehlberghuber; Michael Gautschi; Igor Loi; Germain Haugou; Stefan Mangard; Luca Benini
Publication Year: 2017, Volume: 64, Issue: 9, Pages: 2481 - 2494
Cited by: Papers (108)
Brief Introduction from Author: This paper presents a bandgap reference voltage for high-performance applications, obtaining a minimum measured temperature coefficient of 0.706 ppm/℃ from -25 ℃ to 125 ℃. A simple structure is employed to realize high-order compensation, that is, two bipolar junction transistors and two MOSFETs are operated in their strong-inversion regions with two different bias currents. One bias current is proportional to absolute temperature, and the other is a combination of a proportional-to-absolute-temperature current and a complementary-to-absolute-temperature current. Proper parameters could be designed to make this proposed nonlinear current compensate well for the high-order term in base-emitter voltage of bipolar junction transistors.
Brief Introduction from Author: The current literature about oscillator’s flicker phase noise is either full of conflicting theories or lack of physical insights. In this work, we clarify that they are the second and third harmonic current entering non-resistive paths, causing flicker noise upconversion in nMOS-only and complementary oscillators, respectively. By employing a specific phase-shift range at the gate and drain nodes of the cross-coupled pair, the proposed compact oscillator (0.01mm2) achieves wide-band flicker phase noise suppressing ability with 1/f3 Phase Noise corner of 70kHz and 39% Tuning Range, resulting in the best FoM with normalized TR and area (FoMTA) of −214dB at 1MHz offset.
Brief Introduction from Author: Reference ADC-based timing skew calibration is one category of effective skew calibration strategy in TI-ADC field. However, this approach will suffer from the periodically time-variant input impedance problem if the single-channel reference ADC only operates at a decimated frequency of the full sampling rate, which leads to performance degradation over high input frequency. To address this issue, incorporating the concept of relative-prime, this work proposes a further improved correlation-based skew calibration strategy. A no-digital-calibration-assisted time-interleaved reference ADC (TI-RADC) is employed to detect the skew information among channel ADCs in TI-ADC while the digital backend aligns the channel ADCs with each other to complete the skew correction. This work theoretically demonstrates that with a proper parameters setting, the non-ideal factors of TI-RADC would not affect the skew calibration of TI-ADC. In addition, a recommended TI-RADC implementation structure together with a 13-bit, 8-way, 2-GS/s prototype TI-ADC is presented to verify the proposed skew calibration strategy. Measurement results well validate the correctness of the proposed calibration strategy and demonstrate that the use of TI-RADC gives 20 dB and 5.6 dB improvement on SFDR and SNDR, respectively.
Brief Introduction from Author: RF energy harvesting (RFEH) is an attractive solution for powering internet of things (IoT) applications such as wearable devices. The main challenge in RFEH is to perform efficient rectification of low amplitude AC signals, and the transistor threshold voltage is a key factor that affects the performance of rectifiers. This paper presents a novel RF-DC power converter with a compensation technique that reduces the effective threshold voltage of rectifying devices using dynamic and static self-compensation simultaneously. Furthermore, a design procedure based on MOSFET modeling is detailed, allowing the optimization of the rectifier as a function of the number of stages and size of devices, targeting efficient low voltage/power operation. The experimental results show a sensitivity of -29 dBm on a 100-MΩ resistive load, which is better than previously reported works.
Brief Introduction from Author: This work reviews the IC innovations that have contributed to IoT developments. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend; the computing-in-memory technique improves the energy efficiency, and asynchronous spike neural networks (ASNNs) show low power potential. Small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques improve energy efficiency. In addition, this article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC, which can enhance the lifetime of AIoT devices. Finally, novel evaluation criteria are introduced for benchmarking AIoT chips.
Brief Introduction from Author: The local activity theorem and its “pearl”, the edge of chaos, developed by Prof. Chua, complement and enable the practical application of nonlinear dynamics theory. Chua’s local activity theorem is the only tool currently available that allows one to calculate the precise domain of local activity and edge of chaos, where action potentials may occur.
This paper uncovers some unknown neuromorphic dynamics of the Chua Corsage Memristor (CCM), a recent invention of Chua. In this work, we found the conditions for accurately locating the edge of chaos domain of the CCM using its small-signal equivalent circuit parameters. By adding a positive inductance to the CCM, the resulting circuit proffers a beautiful illustration of a second-order system whose nonlinear differential equations exhibit the global dynamics initiated by the sub-critical Hopf bifurcation. More interestingly, this work shows that the CCM plus a positive inductance and a capacitance can generate neuromorphic phenomena, including those from the classic Hodgkin-Huxley equations. The resulting circuit is the simplest known circuit that exhibits not only chaos, but also some well-known neuromorphic signals. This work can provide a theoretical foundation for understanding the generating mechanism of the action potential, and designing various circuits for emulating neurons.
Brief Introduction from Author: High accuracy and low power ADCs with relative low bandwidth are needed in modern sensor interfaces and IoT applications. Successive-approximation-register (SAR) ADCs are good candidates. However, traditional SAR ADCs only have moderate accuracy due to noise and DAC mismatch error. To address these issues and improve the performance, we proposed a first-order active noise-shaping (NS) SAR ADC using a two-capacitor digitally calibrated DAC. Two-capacitor based DAC gives smaller capacitance spread and hence the mismatch can easily be reduced. Furthermore, correlated double sampling (CDS) and correlated level shifting (CLS) were combined to reduce the power consumption. On-chip calibration with reusing all analog circuits gives 13-dB and 16-dB improvement on SNDR and SFDR, respectively. The prototype achieves 82.6-dB SNDR and 91-dB SFDR.
Authors' Information: Xiang Yi, Cheng Wang, Zhi Hu, Jack W. Holloway, Muhammad Ibrahim Wasiq Khan, Mohamed I. Ibrahim, Mina Kim, Georgios C. Dogiamis, Bradford Perkins, Mehmet Kaynak, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, and Ruonan Han
Affiliation: Massachusetts Institute of Technology
Brief Introduction from Authors: There have been increasing interests recently in using advanced semiconductor technologies to fill the terahertz (THz) gap between the conventional electronic and photonic regimes. Now, researchers are seeking answers to not only how well low-cost silicon chips can handle the THz wave, but also what new and practical applications that THz microsystem innovations can bring. In this paper, a team from MIT and their collaborators reviews the state-of-the-art THz silicon chip work for emerging sensing, metrology and communication applications, such as high-resolution imaging, molecular spectroscopy, time keeping, high-speed wireline/wireless communications, and miniaturization of RF tags. These discussions provide readers a sneak peek at the futures of high-speed electronics.
Brief Introduction from Authors: CMOS imagers are increasingly used in applications like mobile phones, surveillance, autonomous vehicles, machine vision. Recently, 3D-stacked CMOS imagers are being employed, exploiting the increased parallelism to further increase the frame rate while maintaining large spatial density. In designing these, choices must be made about the readout architecture and A/D converters, which are critical for the overall performance of a 3D-stacked imager. The paper compares different 3D-stacked imager readout and A/D converter architectures for this specific target. The comparison shows that ramp and incremental Delta-Sigma ADCs perform better compared to cyclic and SAR ADCs in 3D-stacked imagers while still achieving (very) low fixed-pattern noise.
Brief Introduction from Authors: In-memory computing (IMC) is promising for edge AI applications. To further improve the energy efficiency and technology scalability, time-domain (TD) design has been adopted to IMC, due to its analog and digital advantages. However, conventional TD cells have a large area overhead, limiting their energy efficiencies. Therefore, a dual-edge-single-input (DESI) cell is proposed, which utilizes one inverter to implement TD computing. Then, a 12-T IMC cell is developed, whose area has been reduced by 1.2 to 4.6X compared to prior TD designs. Implemented in 40-nm process, the energy efficiency of the proposed marco achieves 537 TOPS/W.
Brief Introduction from Authors: Artificial intelligence deployment at the edge requires efficient implementation of machine learning models with the constraints of low power and small form factor. Compute-in-memory (CIM) based hardware accelerator is a promising solution with improved throughput and energy efficiency as it reduces the data movement on chip and embraces the mixed-signal computing parallelism. Resistive random access memory (RRAM) has been proposed as a promising technology for CIM owing to its multilevel operation, nonvolatility and instant-on inference capability and foundry availability. This paper reviews the recent progress, focusing on the reliability characterization at array level, monolithic 3D integration of RRAM on top of advanced logic node, and enabler for in-situ training. Prospects are discussed to promote endeavors for co-optimization to advance this emerging technology from the devices, the circuits/systems communities.
Brief Introduction from Authors: With the increasing demand for high-speed ADCs in wireline links, loop-unrolling in SAR ADCs has gained popularity for improved speed. Because loop-unrolled SAR ADCs use multiple comparators, the offset mismatch between the comparators severely degrades the SNDR. We address the common-mode voltage variation and the common-mode dependency of thecomparator offset in loop-unrolled SAR ADCs, and propose a common-mode adaptive background offset calibration to prevent offset mismatch between the comparators. The proposed ADC design also exploits the common-mode variation immunity of the proposed calibration scheme to optimize the figure-of-merit. The prototype achieves 42.57-dB SNDR and 22.8-fJ/conversion-step figure-of-merit at 800 MS/s.
Brief Introduction from Authors: For decades, Moore’s law has powered the ever-increasing demand for performance and density in computing systems. However, in advanced technology nodes, transistor leakage dominates the total power, while the limited capacity of on-chip memory leads to frequent off-chip data-access, thereby limiting overall system performance and energy-efficiency. Mature non-volatile memories such as MRAM, can retain data without power, have fast read and write performance, and are highly compact. We discuss key challenges and explore various tradeoffs that arise in designing on-chip MRAM circuits and systems. We also investigate MRAM-based analog in-memory crossbars and stochastic computing for machine learning applications.
Brief Introduction from Authors: Energy efficiency is a priority issue in the further development of AI edge devices. However, the conventional Von Neumann computing architecture imposes a memory wall bottleneck, which consumes large power due to frequent data movement between memory and processing elements. Computing-in-memory (CIM) is a promising candidate to break through the so-called memory-wall bottleneck by performing computation within the memory macro. This paper outlines the background, trends, and challenges involved in the development of SRAM-CIM macros, which provide unlimited endurance and compatibility with state-of-the-art logic processes. This paper also reviews recent silicon-proven SRAM-CIM macros designed for logic and multiplication-accumulation (MAC) operations.
Brief Introduction from Authors: RFDACs are among the hottest circuits in wireless but must meet tough requirements in power efficiency, integration and wideband operation. RFDACs require sophisticated on-chip matching networks of inductors or transformers, which occupy a lot of precious silicon area and carry large DC currents. Also, their backoff efficiency is not high. The matching network transformer, which has now many windings, is placed directly above the RFDAC switching transistors which can engage the coils intact with the modulation. The multi-port transformer and its interconnects with transistors are carefully designed with EM tools. 8x analog linear interpolation enhances bandwidth. The area got reduced by around 40% while delivering 17.5dBm power at 2.4GHz. The first 7 replicas are suppressed.
Brief Introduction from Authors: Phase-locked loops play a critical role in communications, computing, and data converters. With greater demands for bandwidth efficiency in wireless and wireline transceivers, the maximum tolerable jitter of PLLs has fallen into the sub-100-femtosecond range. Similarly, analog-to-digital converters require extremely low clock jitters as they push for higher performance. These trends inevitably raise the PLL power consumption, potentially making it a significant part of the system's power budget. This paper predicts alarming trends. It is shown that, even if only the oscillator power is considered, jitter values of a few tens of femtoseconds will translate to watts of power.
Selected paper: A Novel Topology of Coupled Phase-Locked Loops
Selected paper: Universal Frequency-Domain Analysis of N-Path Networks
Selected paper: High-Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization
