Ising-CIM: Advancing Ising Accelerators for Combinatorial Optimization Problems with Compute-in-Memory Design Approach

Combinatorial optimization problems (COPs) find applications in real-world scientific, industrial, and societal scenarios. Such COPs are computationally NP-hard, and an exhaustive brute-force search using the traditional von-Neumann computing approach for the optimal solution becomes untenable as the COP size increases. To expedite the COP computation, non- traditional computing formalism utilizing the Ising model is being investigated. An Ising model abstracts the spin dynamics in a ferromagnet wherein the spins are orientated to reach the minimum energy state, representing the optimum COP solution. Previous Ising designs utilized dedicated annealing processors or additional digital arithmetic circuits next to the memory bitcells. These custom circuits or processors cannot be repurposed for other non-COP applications, incurring significant area and power overhead.

In this talk, I will present a reconfigurable and scalable compute-within-memory approach for Ising computation. This area-efficient approach repurposes existing embedded memory bitcell columns and peripheral circuits to perform analog domain Hamiltonian calculations on the bitlines, significantly minimizing area and power overhead. I will present the Silicon hardware results and discuss how the Ising-CIM approach can be adopted to speed up the COP solvers energy-efficiently.