Power Management Techniques for Secure Integrated Circuit Design

Cryptographic cores such as Advanced Encryption Standard (AES) protect sensitive data algorithmically but are vulnerable to attacks using side-channel information. Malicious attackers can analyze a crypto-core’s power consumption and EM emission (called side channel leakage) while encrypting and revealing the sensitive key of the crypto-core non-invasively and at a low cost. Several approaches have been explored to improve the security robustness against these side-channel attacks (SCA). Among these techniques, power management-based techniques are very promising as they directly alter the current and EM signatures to weaken the correlations between the compute activity and current/EM signatures.
In this seminar, I shall provide an overview of the recent power management techniques for SCA resilience. I shall present our ongoing work on power management-based techniques such as (i) Galvanic isolation which separates the encryption current loop from the external VCC/VSS pins completely providing orders of magnitude SCA improvement, (ii) Power delivery approaches against fine-grain EM SCAs (iii) Voltage stacking utilizing single current loop for multiple compute activities thereby reducing the correlation between the current/EM loops and underlying compute activity. Finally, I will conclude the seminar by highlighting the SCA issues arising from the adoption of imminent power delivery technologies such as buried power rails and back-side power delivery in advanced CMOS technologies.