CASS-Wide Webinar Talk V: "AI-RISC: Scalable RISC-V Processor with Artificial Intelligence (AI) extensions for IoT Edge Applications"
AI-RISC is a scalable RISC-V processor developed using hardware, ISA (Instruction Set Architecture), and software co-design methodology to extend the open-source RISC-V architecture for accelerating edge AI applications. AI-RISC tightly integrates hardware accelerators as AI functional units (AFU) inside the RISC-V processor pipeline to allow seamless processing of both AI and non-AI tasks on the same hardware. AI-RISC also extends the RISC-V ISA with custom instructions which directly target the added AFUs and expose the hardware functionality to software programmers. Additionally, AI-RISC generates a complete software stack including compiler, assembler, linker, simulator, and profiler while preserving the high-level programming abstraction offered by popular AI domain-specific languages and frameworks like TensorFlow, PyTorch, MXNet, Keras, etc. AI-RISC accelerates the processing of vector-matrix multiply (VMM) kernel by 17.63x and of ResNet-8 neural network model from industry standard MLPerf Tiny benchmark by 4.41x compared to RISC-V processor baseline. AI-RISC also outperforms the state-of-the-art Arm Cortex-A72 IoT edge processor by 2.45x on average over the complete MLPerf Tiny inference benchmark. Additionally, AI-RISC provides 3.93x improvement in energy-efficiency over the baseline RISC-V processor and 11.49x energy-efficiency improvement over state-of-the-art Gemmini systolic array accelerator.
This talk will take place on 15 February 2023 at 9:00 AM EST (-5:00 UTC) and features a talk by Mircea R. Stan titled "AI-RISC: Scalable RISC-V Processor with Artificial Intelligence (AI) extensions for IoT Edge Applications".
Registration for this series is entirely free and will be limited to the first 1000 registrants per event. If you cannot register, you can also attend the webinar via Facebook Live or access the webinar recording on the IEEE CASS Resource Center.
Mircea R. Stan is teaching and doing research in the areas of AI hardware, Processing in Memory, Cyber-Physical Systems, Computational RFID, spintronics, and nanoelectronics. Since 1996 he has been with the ECE Department at UVa, where he is now the Virginia Microelectronics Consortium (VMEC) endowed chair. He received the 2018 Influential ISCA Paper Award and was a co-author on best paper awards at ASILOMAR19, LASCAS19, SELSE17, ISQED08, GLSVLSI06, ISCA03 and SHAMAN02 and IEEE Micro Top Picks in 2008 and 2003. Prof. Stan is a fellow of the IEEE.