Title
Presentation Type
Webinar
CASS-Wide Webinar XXIV: Design of DTC-Assisted High Performance Fractional-N PLLs
Presenter
Presentation Menu
Abstract
Design of DTC-Assisted High Performance Fractional-N PLLs
High performance fractional-N phase-locked loops (PLLs) are essential elements of any advanced electronic systems. In recent years, both analog and all-digital PLLs employing DTC-assisted phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques to achieve low jitter, low fractional spurs, and low power operation. Both analog circuits design and digital calibration techniques will be reviewed in detail. In addition, complete low-jitter LO chain design examples are demonstrated for WLAN and 5G mm-wave cellular applications.
Description
This talk will take place on 12 November 2024 at 09:00 AM EST (-5:00 UTC) and features a talk by Wanghua Wu, titled "Design of DTC-Assisted High Performance Fractional-N PLLs".
Registration for this series is entirely free and will be limited to the first 1000 registrants per event. If you cannot register, you can also attend the webinar via LinkedIn Live or access webinar recordings on the IEEE CASS Resource Center.
Registration for this series is entirely free and will be limited to the first 1,000 registrants per event. If you cannot register, you can also attend the webinar via LinkedIn Live. Following the webinar, the recording will be available on the CASS Resource Center and as a lesson in the CASS Microlearning (CASS MiLe) e-learning platform. In CASS MiLe, interested practitioners can learn through short didactic units (micro-lessons) with practical questions, and upon lesson completion, learners receive digital badges/certificates.