CASS-Wide Webinar XI: Universalization in IC Design by CASS (UNIC-CASS) - Focused Lecture

This talk will take place on 16 August 2023 at 9:00 AM EDT (-4:00 UTC) and features a focused lecture from José M. de la Rosa, Duy-Hieu Bui, Sergio Bampi, Yongfu Li, and the CASS VP - Education and Communications, Fakhrul Zaman Rokhani, presenting on the Universalization in IC Design by CASS (UNIC-CASS) Program. 

Registration for this series is entirely free and will be limited to the first 1000 registrants per event. If you cannot register, you can also attend the webinar via LinkedIn Live or access the webinar recording on the IEEE CASS Resource Center and IEEE Learning Network (ILN).

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Agenda

• 9.00 -9.05: Welcome & Introductions (Fakhrul Zaman Rokhani, VP - Education & Communications)
• 9.05-9.10: UNIC-CASS Program Overview (Jose De La Rosa, UNIC-CASS Project Sponsor) 
• 9.10-9.20: Education in UNIC-CASS (Dui-Hieu Bui, UNIC-CASS Team Lead)
• 9.20-9.30: Mentoring Design-to-Tapeout  (Sergio Bampi, UNIC-CASS Team Lead)
• 9.30-9.40: Chip Test/Bring-up (Yongfu Li, UNIC-CASS Team Lead)
• 9.40-9.55: Q&A
• 9.58-10.00:  Closing Remarks

Speaker Bios

José M. de la Rosa
José M. de la Rosa received the M.S. degree in Physics in 1993 and the Ph.D. degree in Microelectronics in 2000, both from the University of Seville, Spain. He works at IMSE, where he served as vice-director since February 2018 to March 2023, and he is also a Full Professor at the Dept. of Electronics and Electromagnetism of the University of Seville. Since April 2023, he is the Director of the Office of International Projects of the University of Seville. His main research interests are in the field of analog and mixed-signal integrated circuits, especially high-performance (sigma-delta) data converters, including analysis, behavioral modeling, design and design automation of such circuits. Dr. de la Rosa is an IEEE Fellow, Member-at-Large of the IEEE-CASS Board of Governors (BoG) for the 2023-2025 term and he has been appointed as Editor-in-Chief for the IEEE Transactions on Circuits and Systems -- I: Regular Papers in 2024-2025.

Duy-Hieu Bui
Duy-Hieu Bui received a B.Sc. degree in Electronics Telecommunication Technology from VNU University of Engineering and Technology (VNU-UET) in 2010; an M.Sc. degree in Network and Telecommunications from University of Paris-Sud XI in 2012; and a Ph.D. degree in Nanotechnology and Nanoelectronics from University Grenoble Alpes, France in 2019. He is working as a research engineer at the VNU-key Laboratory for Smart Integrated Systems (SISLAB), VNU-UET. He previously worked at SISLAB, VNU-UET (2010-2015) on VLSI design for multimedia applications, and at CEA-Leti, MINATEC, France (2015-2017) on low-power security hardware and hardware security. He has been a principal engineer in various projects on low-power hardware design for multimedia, security, and artificial intelligence at SISLAB including VENGME, ADEN4IOT, and SCAI. His research interests include hardware/software co-design and verification, embedded systems, low-power solutions for artificial intelligence, VLSI system/circuit designs for information security, and hardware security.

Sergio Bampi
Sergio Bampi received a B.Sc in Electronics Engineering and a B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS, 1979), and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Digital Systems and Microelectronics mixed-signal design fields at the Informatics Institute, member of the faculty since 1986. He served as Graduate Program Coordinator (PGMICRO, 2003-2007), head of research group and projects, technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2006). He is a former member of HP Inc. technical staff, and a visiting research faculty at Stanford University (1998-99) in the USA. His research interests are in the area of IC design, ultra-low power digital design, dedicated complex algorithms, architectures, and ASICs for image and video processing, RF CMOS design, and mixed signal IC design for IoT. He has co-authored more than 440 papers in these fields and in MOS devices and EDA. He is a senior member of IEEE, SBC, and SBMICRO societies. He was Technical Program Chair of IEEE SBCCI Symposium (1997, 2005), SBMICRO (1989, 1995), IEEE LASCAS (2013), VARI 2016 Workshops and Conferences.

Yongfu Li
Yongfu Li received the B.Eng. and Ph.D. degrees from the Department of Electrical and Computing Engineering, National University of Singapore (NUS), Singapore. He is currently an Associate Professor with the Department of Micro and Nano Electronics Engineering and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, China. He was a research engineer with NUS, from 2013 to 2014. He was a senior engineer (2014-2016), principal engineer (2016-2018) and member of technical staff (2018-2019) with GLOBALFOUNDRIES, as a Design-for-Manufacturability (DFM) Computer-Aided Design (CAD) research and development engineer. His research interests include analog/mixed signal circuits, data converters, power converters, biomedical signal processing with deep learning technique and DFM circuit automation. Dr. Li received the Singapore Economic Development Board GLOBALFOUNDRIES Graduate Scholarship. He is currently serving as the Region 10 IEEE-CASS Board of Governors (BoG) for the 2023-2025 term.