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Announcing the sixth talk in the CASS-Wide Webinar Program

The sixth webinar will be on 15 March at 3:00 PM EDT.
3 months 3 weeks ago
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The IEEE CAS Society strives to serve our members' different needs and interests. The new CASS-wide webinar program delivers high-quality talks on the field of interest of the circuit and systems community. As part of the society’s plan for image enhancement through continuous education, the aim is to:

  1. Feature prominent CASS researchers of multidisciplinary nature.
  2. Connect students and early career professionals with prominent CASS researchers and authors.
  3. Promote and preserve CAS knowledge, and enrich the current educational portfolio of the Society.
  4. Enhance the visibility of the IEEE CAS Society.

The webinar series will feature one lecturer a month. Registration is free for all webinars. If you cannot attend the "live" virtual events, the presentations will be available at the IEEE CASS Resource Center after the event.
The webinars will be processed and made available to the community through the CASS Microlearning (CASS MiLe) platform, where interested learners can expand their knowledge and receive credit for reaching proficiency.

Upcoming Webinar

15 March 2023 at 3:00 PM EDT (UTC -4:00) 
Speaker - Vivek De
"Attack-Resistant Energy-Efficient SoCs for Smart and Secure Cyberphysical Systems"

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Talk Abstract
"Attack-Resistant Energy-Efficient SoCs for Smart and Secure Cyberphysical Systems"

SoC design challenges and opportunities for smart and secure cyberphysical systems in the world of Internet-of-Things (IoT) are presented, focusing on two distinct areas: (1) how to deliver uncompromising performance and user experience while minimizing energy consumption, and (2) how to provide cryptographic-quality “roots of trust” in silicon and resistance to physical side channel attacks with minimal overhead. SoC designs that span a wide range of performance and power across diverse platforms and workloads, and achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS, are discussed. Techniques to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations are presented. True Random Number Generator (TRNG) and Physically Unclonable Function (PUF) circuits, the two critical silicon building blocks for generating dynamic and static entropy for encryption keys and digital fingerprints, respectively, are discussed. Power and electromagnetic physical side channel attack detection and mitigation techniques for enabling robust hardware security are also presented.

Speakers Biography
Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for leading and inspiring long-term research in future circuit technologies and design techniques for system-on-chip (SoC) designs with focus on energy efficiency. He has 346 publications in refereed international conferences and journals with a citation H-index of 85, and 240 patents issued with 25 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He is the recipient of the 2019 IEEE Circuits and System Society (CASS) Charles A. Desoer Technical Achievement Award for “pioneering contributions to leading-edge performance and energy-efficient microprocessors & many-core system-on-chip (SoC) designs” and the 2020 IEEE Solid-State Circuits Society (SSCS) Industry Impact Award for “seminal impact and distinctive contributions to the field of solid-state circuits and the integrated circuits industry”. He received the 2017 Distinguished Alumnus Award from the Indian Institute of Technology (IIT) Madras. He received a B.Tech from IIT Madras, India, a MS from Duke University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the IEEE.

Past Webinars

All past webinars can be viewed on the IEEE CASS Resource Center, here.

15 February 2023 at 9:00 AM EST (-5:00 UTC) 
Speaker - Mircea R. Stan
"AI-RISC: Scalable RISC-V Processor with Artificial Intelligence (AI) extensions for IoT Edge Applications"

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Talk Abstract
"AI-RISC: Scalable RISC-V Processor with Artificial Intelligence (AI) extensions for IoT Edge Applications"

AI-RISC is a scalable RISC-V processor developed using hardware, ISA (Instruction Set Architecture) and software co-design methodology to extend the open-source RISC-V architecture for accelerating edge AI applications.
AI-RISC tightly integrates hardware accelerators as AI functional units (AFU) inside the RISC-V processor pipeline to allow seamless processing of both AI and non-AI tasks on the same hardware. AI-RISC also extends the RISC-V ISA with custom instructions which directly target the added AFUs and expose the hardware functionality to software programmers. Additionally, AI-RISC generates a complete software stack including compiler, assembler, linker, simulator and profiler while preserving the high-level programming abstraction offered by popular AI domain-specific languages and frameworks like TensorFlow, PyTorch, MXNet, Keras etc. AI-RISC accelerates the processing of vector-matrix multiply (VMM) kernel by 17.63x and of ResNet-8 neural network model from industry standard MLPerf Tiny benchmark by 4.41x compared to RISC-V processor baseline. AI-RISC also outperforms the state-of-the-art Arm Cortex-A72 IoT edge processor by 2.45x on average over the complete MLPerf Tiny inference benchmark. Additionally, AI-RISC provides 3.93x improvement in energy-efficiency over the baseline RISC-V processor and 11.49x energy-efficiency improvement over state-of-the-art Gemmini systolic array accelerator.

Speakers Biography
Mircea R. Stan is teaching and doing research in the areas of AI hardware, Processing in Memory, Cyber-Physical Systems, Computational RFID, spintronics, and nanoelectronics. Since 1996 he has been with the ECE Department at UVa, where he is now the Virginia Microelectronics Consortium (VMEC) endowed chair. He received the 2018 Influential ISCA Paper Award and was a co-author on best paper awards at ASILOMAR19, LASCAS19, SELSE17, ISQED08, GLSVLSI06, ISCA03 and SHAMAN02 and IEEE Micro Top Picks in 2008 and 2003. Prof. Stan is a fellow of the IEEE.

18 January 2023 at 9:00 AM EST (-5:00 UTC) 
Speaker - Alyssa Apsel
"Ubiquitous, Seamless, and Future Proofed: How Wireless Circuits Can Push IoT"

Talk Abstract
"Ubiquitous, Seamless, and Future Proofed: How Wireless Circuits Can Push IoT"

In 2021 the number of IoT devices reached 46 billion, a 200% increase over the number in 2016*.  By 2030 this number is expected to jump to 125 billion.   While the FCC and other regulators have added licensed and unlicensed spectrum across several bands over the past few years to accommodate these new users, the need for increased wireless capacity and radios that can quickly adapt to new standards remains.  Needless to say, the RF circuit designer has a significant role to play in solving these problems. 

As the market continues to grow, regulating bodies in various countries will undoubtedly continue to work to free up and reallocate spectrum and users will continue to find more ways to use that spectrum.  Users will need both short-reach and low-power IoT devices that can operate independently and share spectrum as well as new WiFi and cellular radios that can quickly adapt to new environments and standards.  

In this talk, I will look at two approaches to these related problems that require unconventional radio designs. First, I will look at an approach from the network side, of how to use a hardware support to build functional mesh networks that can communicate point-to-point in a scalable fashion.  Using such radios can reduce communication bottlenecks in centralized systems as well as enable more devices and sensors with greater flexibility.  The second part of the talk will examine how to add flexibility to the RF front end itself to accommodate changing standards and environments while keeping design and circuit costs low.   I will show techniques for both broadband and tunable narrowband systems that can enable flexibility while maintaining high performance.  With these examples, I will discuss the potential for future flexible analog RF designs and the current limits of this approach.  

Speakers Biography
Alyssa Apsel received her B.S. from Swarthmore College in 1995 and her Ph.D. from Johns Hopkins University, Baltimore, MD, in 2002.  She joined Cornell University in 2002, where she is currently the Director of Electrical and Computer Engineering.  Her current research is on the leading edge of ultra-low power and flexible RF interfaces for IoT.  Her group has pioneered the use of coupled oscillators for network synchronization of mesh networks and a variety of techniques for flexible RF systems.  She has authored or co-authored over 100 refereed publications including one book in related fields of RF mixed signal circuit design, ultra-low power radio, interconnect design and planning, photonic integration, and process invariant circuit design techniques resulting in ten patents.  She has received a number of best paper awards and the National Science Foundation CAREER Award in addition to being selected by Technology Review Magazine as one of the Top Young Innovators in 2004.  More recently Professor Apsel served as a Distinguished Lecturer for IEEE CAS from 2018-2019 and was named an IEEE Fellow.

14 December 2022 at 9:00 AM EST (-5:00 UTC) 
Speaker - Zhihua Wang
"Challenges and Design of RF Transceivers for Medical Applications"

Talk Abstract
The demand to make the medical devices smaller and smarter, is one of the driving forces of integrated circuits (ICs) and systems. More specifically, the implantable medical devices (IMD’s), which are fully or partially implanted in the human bodies through surgeries, have imposed even critical technical requirements on the building ICs, especially on the wireless connection ICs. A good trade-off has to been made among the key parameters, including the choice of protocols, carrier frequency, data rate, robustness under various interference, etc, and most importantly, the power consumption. In this lecture, the typical medical application scenarios will be discussed, along with a set of miniature IMD’s which have been implemented based the ultra-low power wireless connection. Then the requirement and challenges of wireless connections in such applications will be analyzed, and the design considerations of ultra-low power RF transceivers will be presented. The circuit design details of the recently published 400/915MHz combo transmitter (TX) IC and 915MHz receiver (RX) IC will be presented to demonstrate the above-mentioned design philosophy. The ultra-low power techniques, including the multi-phase digital power amplifier (DPA) based polar TX, the edge combing TX with open-loop local oscillation (LO) generation, and the sub-sampling phase tracking RX will be presented. Through this lecture, we hope that we can share with the audience our thinking and design practice of ultra-low power RF transceivers for miniature medical devices.

Speakers Biography
Zhihua Wang (FIEEE, FCIE, FCIC) received the B.S., M.S., and Ph.D. degrees in electronic engineering from Tsinghua University, Beijing, China, in 1983, 1985, and 1990, respectively. Since 1997, he has been a Full Professor with Tsinghua University. Since 2000, he has been the Deputy Director of the Institute of Microelectronics. From 1992 to 1993, he was a Visiting Scholar at CMU. He was a Visiting at KU Leuven from 1993 to 1994. From September 2014 to March 2015, he was a Visiting Professor at HKUST. He has coauthored 13 books/chapters, over 241 (594) articles in international journals (conferences), over 253 (29) articles in Chinese journals (conferences), and holds 130 Chinese and ten U.S. patents. His current research mainly focuses on CMOS RFIC and biomedical applications, involving RFID, PLL, low-power wireless transceivers, and smart clinic equipment combined with leading edge RFIC and digital image processing techniques. He was an AdCom Member of the IEEE SSCS from 2016 to 2019. He was a Technology Program Committee Member of the IEEE ISSCC from 2005 to 2011. Since 2005, he was a Steering Committee Member of the IEEE A-SSCC. He has served as the Chairman of IEEE SSCS Beijing Chapter from 1999 to 2009. He was the Technical Program Chair for A-SSCC 2013. He was a Guest Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC) Special Issue in December 2006, December 2009, and November 2014. During 2019-2020, he has been an Associate Editor in Chief of IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS. He had been an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS during 2016-2019, and IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS during 2010-2013, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS (BioCAS) during 2008-2015, and other administrative/expert committee positions in China’s national science and technology projects. From 2018 to 2019, he was an IEEE SSCS Distinguished Lecturer. Since 2020, he has been an IEEE CASS Distinguished Lecturer.

16 November 2022 at 9:00 AM EST (-5:00 UTC) 
Speaker - Shimeng Yu 
"Recent Progresses of RRAM Compute-in-Memory Prototype Chips"

Talk Abstract
In this presentation, we will present the recent progresses on the compute-in-memory (CIM) prototype chips using the resistive random access memory (RRAM) technology. Mixed-signal RRAM based CIM can process the multiply-accumulate (MAC) functions in deep neural networks efficiently using the integrated analog-to-digital converter (ADC), thus it is regarded as a competitive solution for AI hardware design for edge intelligence. In collaboration with TSMC Corporate Research, we taped out two generations of RRAM CIM macros in TSMC 40 nm process.
The following features are supported in these prototype chips:

  1. Adaptive input sparsity control
  2. Reconfigurable weight precision
  3. Integrated digital compute units
  4. Input-aware on-chip ADC reference
  5. On-chip write-verify controller
  6. Input encoding for embedded security
  7. ADC-less communication between sub-arrays with pulse-width-modulation
  8. In-situ error correction code that preserves the MAC parallelism

Finally, the prospects and challenges of CIM chip design will be summarized. 

Speakers Biography
Shimeng Yu is currently an associate professor of electrical and computer engineering at the Georgia Institute of Technology. He received a B.S. degree in microelectronics from Peking University in 2009, and an M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University.

Prof. Yu’s research interests are the semiconductor devices and integrated circuits for energy-efficient computing systems. His research expertise is on the emerging non-volatile memories for applications such as deep learning accelerator, in-memory computing, 3D integration, and hardware security. Among Prof. Yu’s honors, he was a recipient of the NSF Faculty Early CAREER Award in 2016, the IEEE Electron Devices Society (EDS) Early Career Award in 2017, the ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, IEEE Circuits and Systems Society (CASS) Distinguished Lecturer, and IEEE Electron Devices Society (EDS) Distinguished Lecturer, etc.

Prof. Yu has served many premier conferences as technical program committee, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology and Circuits, IEEE International Reliability Physics Symposium (IRPS), ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), ACM/IEEE International Conference on Computer-Aided-Design (ICCAD), etc.  He is serving an editor for IEEE Electron Device Letters (EDL). He is a senior member of the IEEE.

12 October 2022 at 9:00 AM EDT (-4:00 UTC) 
Speaker - Sorin Cotofana 
"Graphene-Based Computing"

Talk Abstract
In this presentation, we argue and provide Non-Equilibrium Green’s Function Landauer formalism-based simulation evidence that in spite of Graphene’s bandgap absence, Graphene Nanoribbons (GNRs) can provide support for energy-effective computing.  We start by demonstrating that: (i) band gap can be opened by means of GNR topology and (ii) GNR’s conductance can be molded according to some desired functionality, i.e., 2- and 3-input AND, NAND, OR, NOR, XOR, and XNOR, via shape and electrostatic interaction. Afterward, we introduce a generic GNR-based Boolean gate structure composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing the gate inverted Boolean function, and, by properly adjusting GNRs' dimensions and topology, we design and evaluate by means of SPICE simulations inverter, buffer, and 2-input GNR based AND, NAND, and XOR gates. Compared with state-of-the-art graphene FET and CMOS-based counterparts the GNR-based gates outperform its challengers, e.g., up to 6x smaller propagation delay, 2 orders of magnitude smaller power consumption while requiring 1 to 2 orders of magnitude smaller active area footprint than 7nm CMOS equivalents. Finally, to get a better inside into the practical implications of the proposed approach, we present Full Adder (FA) and SRAM cell GNR designs, as they are currently fundamental components for the construction of any computation system. For an effective FA implementation, we introduce a 3-input MAJORITY gate, which apart of being able to directly compute FA's carry-out is an essential element in the implementation of Error Correcting Codes codecs, that outperforms a 7nm CMOS equivalent Carry-Out calculation circuit by 2 and 3 orders of magnitude in terms of delay and power consumption, respectively, while requiring 2 orders of magnitude less area. The proposed FA exhibits 6x smaller delay, 3 orders of magnitude less power consumption while requiring 2 orders of magnitude less area than a 7 nm FinFET CMOS counterpart. However, because of the effective carry-out circuitry, a GNR-based n-bit Ripple Carry Adder, whose performance is linear in the Carry-Out path delay, will be 108x faster than an equivalent CMOS implementation. The GNR-based SRAM cell provides a slightly better resilience to DC-noise characteristics, while performance-wise has a 3x smaller delay, consumes 2 orders of magnitude less power, and requires 1 order of magnitude less area than the CMOS equivalent. These results clearly indicate that the proposed GNR-based approach is opening a promising avenue toward future competitive carbon-based nanoelectronics. 

Speaker's Biography
Currently, I am an Associate Professor with the Computer Engineering Laboratory, Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, The Netherlands. I received the MSc degree in Computer Science from "Politehnica" University of Bucharest, Bucharest, Romania, and the PhD degree in Electrical Engineering from Delft University of Technology, The Netherlands.

I am an IEEE Fellow and a HiPEAC member.

My current research is focused on: (i) unconventional computation paradigms and computation with emerging nano-devices, (ii) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components, and (iii) ageing assessment/prediction and lifetime reliability aware resource management.

I (co-)authored more than 250 papers in peer-reviewed international journals and conferences, received 12 Best Paper Awards in international conferences, e.g., 2016 IEEE/ACM International Symposium on Nanoscale Architectures, 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, and 2001 International Conference on Computer Design.

In the last decade, I have been involved in European Union funded research projects, e.g., i-RISC, 3DIM3, NEMSIC, as Principal Investigator and Work Package Leader.

I served as Associate Editor for IEEE Transactions on CAS I (2009-2011), IEEE Transactions on Nanotechnology (2008-2014), Microprocessors and Microsystems (2016-2017), and Nano Communication Networks (2010-2014);  Associate Editor in Chief for IEEE Transactions on Nanotechnology (2015 - 2019); Senior Editorial Board Member for IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2016-2017); Steering Committee Member for IEEE Transactions on Multi-Scale Computing Systems (2014-2018); Chair of the Giga-Nano IEEE CASS Technical Committee (2013-2015); and IEEE Nanotechnology Council CASS representative (2013-2014).

I have been actively involved in the organization of numerous international conferences as General Chair (e.g., NANOARCH 2018), Technical Program Committee (TPC) Chair (e.g., NANOARCH 2012), Track Chair, (e.g., ISCAS 2014-2016), Special Sessions Chair, (e.g., ICECS 2016), Workshop Chair, (e.g., ESSCIRC 2013), and TPC Member (e.g., ISCAS, DATE, ARITH, NANOARCH, GLSVLSI).

Currently, I am Editor in Chief for IEEE Transactions on Nanotechnology, Associate Editor for IEEE Transactions on Computers, CASS BoG member (2020-2022), and CASS Distinguished Lecturer (2019-2020).

Presently, I am co-Principal Investigator of the EU FET Open “Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics” (CHIRON) project and my teaching includes MSc Computer Engineering courses Modern Computer Architecture (ET4074), Computer Arithmetic (ET4170), and Processor Design (ET4171).